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DS1318
Parallel-Interface Elapsed Time Counter
2
_____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on any Pin Relative to Ground ......-0.3V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+260°C
Soldering Temperature (reflow) .......................................+260°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP (multilayer board)
Junction-to-Ambient Thermal Resistance (
θJA) ............72°C/W
Junction-to-Case Thermal Resistance (
θJC) .................13°C/W
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VCC
(Note 3)
3.0
3.3
3.6
V
Battery Voltage
VBAT
(Note 3)
1.6
3.3
3.7
V
Logic 1 Voltage
VIH
(Note 3)
0.7 x
VCC
VCC +
0.5
V
Logic 0 Voltage
VIL
(Note 3)
-0.5
+0.3 x
VCC
V
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic 0 Output Current
(VOL = 0.15 x VCC)
IOL
3
mA
Logic 1 Output Current
(VOH = 0.85 x VCC)
IOH
1
mA
SQW, INT Logic 0 Output
(VOL = 0.15 x VCC)
IOLSI
5
mA
Input Leakage
ILI
(Note 4)
1
μA
I/O Leakage
ILO
(Note 5)
-1
+1
μA
Active Supply Current
ICCA
(Note 6)
10
mA
Standby Current
ICCS
(Note 7)
100
150
μA
Battery Input-Leakage Current
IBATLKG
10
100
nA
Power-Fail Voltage
VPF
(Note 3)
2.70
2.97
V
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
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